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Triple damascene formation and quadruple damascene manufacturing technology

机译:三层大马士革形成和四层大马士革制造技术

摘要

The present invention provides integrated circuit fabrication methods and devices wherein triple damascene structures are formed in five consecutive dielectric layers (312, 314, 316, 318 and 320), using two etching sequences. A first etching sequence comprising: depositing a first etch mask layer (322), on the fifth (top) layer (320), developing a power line trench pattern (324) and a via pattern (326) in the first mask layer, simultaneously etching the power line trench pattern (324) and the via pattern (326) through the top three dielectric layers (316, 318, 320), and removing the first etch mask layer. A second etching sequence including: depositing a second etch mask layer (330), on the fifth layer (320) and inside the power line trench (325) formed in the first etching sequence, developing a signal line pattern (332) overlaying the via pattern (327) in the second etch layer, etching the via pattern (327) through the second layer (312), and subsequently etching the via pattern (327) through the first layer (312) while simultaneously etching the signal line trench pattern (332) through the fifth layer (320). The etching sequences result in the formation of a power line trench (325) and a signal line trench (336) with an underlying via hole (340). These trenches and the via hole are simultaneously filled with a conductive material, such as a metal, to form a triple damascene structure including a power line (352) and a signal line (354) having an underlying via plug (356). This triple damascene structure uses three design rules while only requiring two etch mask layers, and only one planarizing or etch back stop to define the interconnect lines. Similar novel techniques can be employed to fabricate a quadruple damascene structure including a power line (450) having an underlying via plug (452) and a signal line (454) with an underlying via plug (456), while using four design rules. The inventive techniques can also be utilized to form similar triple and quadruple damascene structures in a variety of dielectric stacks. In additional embodiments, manufacturing systems (1110) are provided for fabricating IC structures, such as the novel damascene structures. These systems include a controller (1100) which is adapted for interacting with a plurality of fabrication stations (1120, 1122, 1124, 1126, 1128, 1130 and 1132).
机译:本发明提供了集成电路制造方法和器件,其中使用两个蚀刻序列在五个连续的介电层(312、314、316、318和320)中形成三镶嵌结构。第一蚀刻序列包括:在第五(顶层)层(320)上沉积第一蚀刻掩模层(322),同时在第一掩模层中形成电源线沟槽图案(324)和通孔图案(326)。通过顶部的三个介电层(316、318、320)蚀刻电源线沟槽图案(324)和通孔图案(326),并去除第一蚀刻掩模层。第二蚀刻序列包括:在第五层(320)上和在第一蚀刻序列中形成的电源线沟槽(325)内沉积第二蚀刻掩模层(330),形成覆盖通孔的信号线图案(332)在第二蚀刻层中蚀刻图案(327),蚀刻穿过第二层(312)的通孔图案(327),随后蚀刻穿过第一层(312)的通孔图案(327),同时蚀刻信号线沟槽图案( 332)到第五层(320)。蚀刻序列导致形成具有下面的通孔(340)的电源线沟槽(325)和信号线沟槽(336)。这些沟槽和通孔同时填充有诸如金属的导电材料,以形成三重镶嵌结构,该三重镶嵌结构包括电源线(352)和具有下面的通孔插塞(356)的信号线(354)。这种三层镶嵌结构使用三个设计规则,而仅需要两个蚀刻掩模层,并且仅一个平坦化或回蚀停止层就可以定义互连线。在使用四个设计规则的同时,可以采用类似的新颖技术来制造四层镶嵌结构,其包括具有下层通孔插头(452)的电源线(450)和具有下层通孔插头(456)的信号线(454)。本发明的技术还可以用于在各种电介质堆叠中形成相似的三重和四重镶嵌结构。在另外的实施例中,提供制造系统(1110)以制造IC结构,例如新颖的镶嵌结构。这些系统包括控制器(1100),其适于与多个制造站(1120、1122、1124、1126、1128、1130和1132)交互。

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