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POWER CONSUMPTION REDUCING CIRCUIT AND POWER CONSUMPTION REDUCING METHOD USED FOR THE CIRCUIT

机译:降低功耗的电路以及用于该电路的功耗降低方法

摘要

PROBLEM TO BE SOLVED: To provide a power consumption reducing circuit which can read out data from a memory cell continuously and at high rate with low power consumption.;SOLUTION: In cell arrays CA11-CA1n, CB11-CB1n belonging to the same row of (n) pieces of block A300, block B400 making a pair with two groups, when data of blocks of the cell arrays CA11-CA1n of one side is read out, data of blocks of the cell arrays CB11-CB1n are prepared by half. Operation of sense amplifiers of the cell arrays CA11-CA1n, CB11-CB1n at the time of read-out is divided.;COPYRIGHT: (C)2002,JPO
机译:解决的问题:提供一种功耗降低电路,该电路能够以低功耗连续且高速率地从存储单元中读出数据;解决方案:在属于单元阵列的同一行的单元阵列CA11-CA1n,CB11-CB1n中(n)块A300,块B400与两组成对,当读出一侧的单元阵列CA11-CA1n的块的数据时,将单元阵列CB11-CB1n的块的数据准备一半。读出时对单元阵列CA11-CA1n,CB11-CB1n的读出放大器的操作进行了划分。版权所有:(C)2002,JPO

著录项

  • 公开/公告号JP2002298583A

    专利类型

  • 公开/公告日2002-10-11

    原文格式PDF

  • 申请/专利权人 NEC MIYAGI LTD;

    申请/专利号JP20010105306

  • 发明设计人 TAKADA HIROSHI;

    申请日2001-04-04

  • 分类号G11C11/409;G11C11/401;

  • 国家 JP

  • 入库时间 2022-08-22 00:59:57

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