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High performance PNP bipolar device fully compatible with CMOS process
High performance PNP bipolar device fully compatible with CMOS process
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机译:高性能PNP双极器件,与CMOS工艺完全兼容
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摘要
A pnp bipolar junction transistor is formed with improved emitter efficiency by reducing the depth of the p well implant to increase carrier concentration in the emitter and making the emitter junction deeper to increase minority lifetime in the emitter. The high gain BJT is formed without added mask steps to the process flow. A blanket high energy boron implant is used to suppress the isolation leakage in SRAM in the preferred embodiment.
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