Apparatus, method and system for a controllable pulse clock delay arrangement to control functional race margins in a logic data path

摘要

A controllable pulse-clock-delay apparatus for use with an integrated circuit, the controllable pulse-clock-delay apparatus including an input pulse clock terminal that is adapted to receive an input pulse clock, an output pulse clock terminal, a controllable delay arrangement that is coupled to the input pulse clock terminal, and that is adapted to output an output pulse clock at the output pulse clock terminal, and a feedback arrangement coupling the output pulse clock to the controllable delay arrangement so that another output pulse clock is based on the input pulse clock and the output pulse clock.