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Method and apparatus for creating testable circuit designs having embedded cores

机译:用于创建具有嵌入式内核的可测试电路设计的方法和装置

摘要

A computer-implemented method and apparatus for creating a testable circuit design that includes one or more embedded cores. The method includes identifying an embedded core within the circuit design; associating certain pins of the embedded core with pins of the circuit design; and inserting into the circuit design access circuitry coupling the certain connection pins of the embedded core to the associated pins of the circuit design. The method further includes providing test vectors for the embedded core; and generating test vectors for the circuit design by mapping the core test vectors applicable to the certain pins of the embedded core to the associated pins of the circuit design. The cores within the circuit design can then be tested after manufacture by applying the design test vectors to the circuit design.
机译:一种用于创建包括一个或多个嵌入式内核的可测试电路设计的计算机实现的方法和装置。该方法包括识别电路设计内的嵌入式核;以及将嵌入式内核的某些引脚与电路设计的引脚相关联;并将耦合到嵌入式内核的某些连接引脚到电路设计的相关引脚的电路设计插入电路。该方法还包括提供用于嵌入式核的测试向量;以及通过将适用于嵌入式内核某些引脚的内核测试矢量映射到电路设计的相关引脚,生成用于电路设计的测试矢量。然后,可以在制造后通过将设计测试向量应用于电路设计来测试电路设计中的核心。

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