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Method and apparatus for creating testable circuit designs having embedded cores
Method and apparatus for creating testable circuit designs having embedded cores
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机译:用于创建具有嵌入式内核的可测试电路设计的方法和装置
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摘要
A computer-implemented method and apparatus for creating a testable circuit design that includes one or more embedded cores. The method includes identifying an embedded core within the circuit design; associating certain pins of the embedded core with pins of the circuit design; and inserting into the circuit design access circuitry coupling the certain connection pins of the embedded core to the associated pins of the circuit design. The method further includes providing test vectors for the embedded core; and generating test vectors for the circuit design by mapping the core test vectors applicable to the certain pins of the embedded core to the associated pins of the circuit design. The cores within the circuit design can then be tested after manufacture by applying the design test vectors to the circuit design.
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