Method for fabricating lateral PNP heterojunction bipolar transistor and related structure

摘要

According to one embodiment, a dielectric layer is deposited over an n-well. For example, the dielectric layer can be silicon dioxide, silicon nitride or a low-k dielectric. Subsequently, the dielectric layer is etched to fabricate an opening over the n-well. An interfacial oxide layer is next formed in the opening. Thereafter, a semiconductor layer, which can comprise amorphous silicon for instance, is deposited over the interfacial oxide layer. A layer of silicon-germanium is then grown over the semiconductor layer. In another embodiment, a dielectric layer is deposited over an n-well. The dielectric layer is then etched to fabricate a gap over the n-well between the dielectric layer and an oxide region. Subsequently, a layer of silicon-germanium is grown in the gap. The gap has a gap width which satisfies a pre-determined relation to the thickness of the layer of silicon-germanium.