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Method for functional verification of VLSI circuit designs utilizing reusable functional blocks or intellectual property cores
Method for functional verification of VLSI circuit designs utilizing reusable functional blocks or intellectual property cores
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机译:利用可重用功能块或知识产权核对vLSI电路设计进行功能验证的方法
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摘要
Computer-assisted apparatus/method functionally verifies circuit design through automatic generation of verification rules from reusable functional block or IP core using logic simulator and input stimuli. Rule base captures set of design states or scenarios.
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