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Integrated circuit polysilicon resistor having a silicide extension to achieve 100 metal shielding from hydrogen intrusion

机译:具有硅化物扩展的集成电路多晶硅电阻器,可实现100%的金属屏蔽氢侵入

摘要

A stable, high-value polysilicon resistor is achieved by using a silicide layer that prevents diffusion of hydrogen into the resistor. The resistor can also be integrated into a salicide process for making FETs without increasing process complexity. A polysilicon layer with a cap oxide is patterned to form FET gate electrodes and the polysilicon resistor. The lightly doped source/drains, insulating sidewall spacers, and source/drain contacts are formed for the FETs. The cap oxide is patterned to expose one end of the resistor, and the cap oxide is removed from the gate electrodes. A refractory metal is deposited and annealed to form the salicide FETs and concurrently to form a silicide on the end of the resistor. The unreacted metal is etched. An interlevel dielectric layer is deposited and contact holes with metal plugs are formed to both ends of the resistor. A metal is deposited to form the first level of metal interconnections, which also provides contacts to both ends of the resistor. The metal is also patterned to form a metal shield over the resistor to prevent hydrogen diffusion into the resistor. In this invention the spacing between the metal portions contacting the ends of the resistor is aligned over the silicide on the resistor to provide 100% shielding from hydrogen diffusion into the resistor.
机译:通过使用防止氢扩散到电阻器中的硅化物层,可以获得稳定的高价值多晶硅电阻器。电阻器也可以集成到自对准硅化物工艺中,以制造FET,而不会增加工艺复杂性。图案化具有帽氧化物的多晶硅层以形成FET栅电极和多晶硅电阻器。为FET形成了轻掺杂的源极/漏极,绝缘侧壁隔离层和源极/漏极触点。图案化帽氧化物以暴露电阻器的一端,并且从栅电极去除帽氧化物。沉积难熔金属并进行退火以形成自对准硅化物FET,并同时在电阻器的末端形成硅化物。未反应的金属被蚀刻。沉积层间电介质层,并且在电阻器的两端形成带有金属塞的接触孔。沉积金属以形成金属互连的第一级,该第一级还提供到电阻器两端的触点。还对金属进行构图,以在电阻器上方形成金属屏蔽层,以防止氢扩散到电阻器中。在本发明中,与电阻器的端部接触的金属部分之间的间隔在电阻器上的硅化物上方对准,以提供100%的屏蔽,防止氢扩散到电阻器中。

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