Designing memory for testability to support scan capability in an asic design

摘要

A system and method are presented for incorporating boundary scan test capability in an embedded memory. Existing half-latches within the memory are augmented to create full-latches, configurable as a scan register. This requires substantially less circuitry than if the entire scan register was created separately. Furthermore, separate signal paths are maintained for the functional signals and for the boundary scan data. Therefore, the boundary scan logic does not contribute additional propagation delay to the functional signals. Also, because the test circuitry is within the memory (rather than external to it), placing and routing of the scan circuitry is much less complicated than with previous methods.