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Level shifter for ultra-deep submicron CMOS designs
Level shifter for ultra-deep submicron CMOS designs
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机译:适用于超深亚微米CMOS设计的电平转换器
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摘要
New level shifting circuits, one using dynamic current compensation and one using dynamic voltage equalization, are described. An input swings between a low supply and ground. An output swings between a high supply and ground. An inverter input is connected to the input of the level shifting circuit to form an inverted level shifting input. A first NMOS transistor has the gate tied to the level shifting input and the source tied to ground. A first PMOS transistor has the gate tied to the level shifting output, the source tied to the high supply, and the drain tied to the first NMOS drain. A second NMOS transistor has the gate tied to the inverted level shifter input, the source tied to the ground, and the drain tied to the level shifting output. A second PMOS transistor has the gate tied to the first NMOS drain, the source tied to the high supply, and the drain is tied to the level shifting output. A third NMOS transistor has the gate tied to the first NMOS drain, v source tied to the level shifting input, and the drain tied to the level shifting output. A fourth NMOS transistor has the gate tied to the second NMOS drain, the source tied to the inverted level shifting input, and the drain tied to the first NMOS drain.
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