Semiconductor memory device requiring performance of plurality of tests for each of plurality of memory circuits and method for testing the same

摘要

A test pattern generation circuit for generating a test pattern for a disturb test is provided in an SDRAM. A test pattern generated in the test pattern generation circuit is supplied to a circuit relating to a selected bank and a test pattern is supplied from a tester to a circuit relating to other bank. As more than one test can be simultaneously performed, test time can be reduced.