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Edge growth heteroepitaxy processes with reduced lattice mismatch strain between a deposited semiconductor material and a semiconductor substrate

机译:边缘生长异质外延工艺,可降低沉积的半导体材料与半导体衬底之间的晶格失配应变

摘要

Semiconductor devices that include mismatched lattice crystal interfaces are produced by edge growth heteroepitaxy from a crystal with a small surface area to decrease crystal mismatch strain, achieving a crystal with reduced displacement faults. Mismatched crystal lattices are also deposited on a deformable thin membrane of semiconductor material to reduce strain in growing crystal and to reduce displacement faults to achieve a monolithic crystal structure.
机译:包括不匹配晶格晶体界面的半导体器件是通过边缘生长异质外延从具有小表面积的晶体中产生的,以减小晶体失配应变,从而获得具有减少的位移缺陷的晶体。不匹配的晶格也沉积在半导体材料的可变形薄膜上,以减少晶体生长中的应变并减少位移缺陷,从而获得单片晶体结构。

著录项

  • 公开/公告号US6417077B1

    专利类型

  • 公开/公告日2002-07-09

    原文格式PDF

  • 申请/专利权人 MOTOROLA INC.;

    申请/专利号US20000499285

  • 发明设计人 JOHN J. STANKUS;

    申请日2000-02-07

  • 分类号H01L212/00;

  • 国家 US

  • 入库时间 2022-08-22 00:46:59

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