Vertical interdigitated metal-insulator-metal capacitor for an integrated circuit

摘要

A substantially vertical interdigitated plate capacitor, formed in interlayer dielectric material between upper and lower interconnect layers of conductors in an integrated circuit, comprising a lower plate that has at least one U-shaped portion and a horizontal portion connected to an upper edge of the U-shaped portion. The capacitor's upper plate also has at least one U-shaped portion positioned within the interior of the lower plate's U-shaped portion and a horizontal portion connected to an upper edge of each vertically extending leg. The integrated circuit incorporating the capacitor comprises a via connection having a U-shaped layer extending between the conductors of the relatively upper and relatively lower interconnect layers and is formed simultaneously with one of the U-shaped portions of the capacitor plates.