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Semiconductor integrated circuit device capable of performing operational test for contained memory core at operating frequency higher than that of memory tester
Semiconductor integrated circuit device capable of performing operational test for contained memory core at operating frequency higher than that of memory tester
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机译:能够以高于存储器测试器的工作频率对所包含的存储器核心执行操作测试的半导体集成电路器件
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摘要
A test interface circuit carries out an operational test based on a signal input to test pin terminals by directly accessing a DRAM core. A frequency multiplication circuit generates an internal test clock signal by multiplying the frequency of an external test clock signal input to the test pin terminal. A data shifter shifts read data from the DRAM core which operates according to the internal test clock signal in a test mode by N clock cycles (N is an integer of at least 0 determined by column latency) of the internal test clock signal to output the read data from the test pin terminals in synchronization with the external clock test signal.
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