Bus architecture and protocol with quadruplicate processing capacity

摘要

"BUS ARCHITECTURE AND PROTOCOL WITH QUADRUPLICED PROCESSING CAPACITY". It is a bidirectional multipoint processor bus that is connected to a plurality of bus agents. The speed of data transfer on the bus can be increased by operating the bus in a signaling mode with multiplied processing capacity, in which multiple information elements are operated on the bus by a controlling agent at a rate that is multiple of the pulse frequency. bus synchronization. The controlling agent also activates a validation to identify sampling points for the information elements. The information elements for a request can be operated, for example, using a signaling mode with double processing capacity, in which two information elements are operated during a cycle of the bus synchronization pulse. The data elements for a data line transfer can be operated, for example, using a signaling mode with quadruple processing capacity, in which four data elements are activated during a cycle of the bus synchronization pulse. Multiple validation signals can be temporarily activated in an offset or offset arrangement to reduce the frequency of validation signals. The sampling symmetry can be improved by using only one type of edge (for example, both rising and falling edges) of the validation signals to identify the sampling points.