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SELF-ALIGNED PRECISE HIGH SHEET RHO RESISTOR FOR MIXED-SIGNAL APPLICATION

机译:用于混合信号应用的自校准精密高阻Rho电阻

摘要

A new method is provided for the creation of a resistiveload in a semiconductor device whereby the semiconductor devicefurther contains gate electrodes and a capacitor. Fieldisolation regions separate the active areas; a thin layer ofgate oxide is created over these active regions. A first layerof dielectric is deposited, used for the gate electrode, for thebottom plate of the adjacent capacitor and for the resistor ofhigh ohmic value. The gate poly is doped (in the first layer ofdielectric); optionally the bottom plate of the capacitor can bedoped. A second dielectric layer is deposited for the dielectricof the capacitor; a third layer of dielectric is deposited,patterned and etched to form the capacitor top plate. Thecapacitor (dielectric and bottom plate), poly gates and the loadresistor are patterned; the LDD regions for the transistors arecreated. The (gate, capacitor, resistor) spacers are formed,during and as part of the etch of the gate spacers a resistivespacer (called spacer since it serves to space or separate thetwo contact points of the resistor) is formed. The source/drainimplants for the gate electrodes are performed therebyconcurrently performing (self-aligned, due to the resistorspacer) implants for the contact regions of the resistor. Allcontacts (gate poly, source/drain and two contact points on theresistor) are salicided to achieve lower contact resistance.
机译:提供了一种用于创建电阻的新方法加载到半导体器件中,从而使半导体器件还包含栅电极和电容器。领域隔离区域将活动区域分开;薄薄的一层在这些有源区上方形成栅极氧化物。第一层沉积了一定数量的电介质,用于栅电极,用于相邻电容器的底板和电阻的高欧姆值。栅极多晶硅被掺杂(在第一层电介质);可选地,电容器的底板可以是掺杂。沉积用于电介质的第二电介质层电容器的;沉积第三层电介质,图案化并蚀刻以形成电容器顶板。的电容器(电介质和底板),多晶硅栅极和负载电阻图案化;晶体管的LDD区域为创建。形成(栅极,电容器,电阻器)垫片,在栅隔离层蚀刻过程中以及蚀刻过程中,电阻性分隔符(称为分隔符,因为它用于分隔或分隔电阻的两个触点)。源极/漏极从而进行栅电极的注入同时执行(由于电阻而自对准垫片)注入电阻的接触区域。所有接触点(栅极多晶硅,源极/漏极和两个接触点)电阻化)以降低接触电阻。

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