Edge triggered D-flip-flop circuit

摘要

In the present invention, an edge-triggered D-Flip-Flop circuit with a master/slave configuration is disclosed. The master circuit (MA) comprises only one master switch (T1) controlled by a clock signal (C¯) and followed by a first inverter (I1). The slave circuit (SL) comprises a slave switch (T2) followed by a second inverter (I2) and a regenerative feedback-loop (I3, T3). Master and slave switches (T1, T2) can easily be realised using pass-transistors thus achieving small chip area. The Flip-Flop can easily be amended by set and reset means (T4, T5) and is preferably suitable for mass applications like memory and microprocessor chips.