Circuit for forming ratio of two input signals has delta-sigma modulator with comparator formed by clock edge triggered D-flip-flop and uses variable reference signal

摘要

The circuit has a delta-sigma modulator, whereby the difference between an input signal (U1) and a reference signal (U2) or inverted reference signal is applied to an integrator input; the integrator (I) output feeds a comparator (DFF) producing the circuit output and controlling a switched reference signal inverter (INV). The reference signal is variable and the comparator is formed by a clock edge triggered D-flip-flop.