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Fractional-Enphase Synchronous Loop with Self-correcting Fractional Delay Element

机译:具有自校正分数延迟元素的分数相同步环路

摘要

The delay interval for the feedback signal is increased if a small fractional divisor (1/2) resulting in a lagging phase relationship or a large fractional divisor ( 1/2) resulting in a leading phase relationship is detected. Become; Self-correcting fractional delay element that controls the PLL feedback signal in a reduced manner when a small fraction divisor (1/2) resulting in a fast relationship or a large fraction divisor ( 1/2) resulting in a ground relationship is detected. A fractional-N phase locked loop (PLL) with a delay lineloop (DLL).
机译:如果检测到导致相位关系滞后的小分数因数(<1/2)或导致超前相位关系的大分数因数(> 1/2),则会增加反馈信号的延迟间隔。成为;当检测到导致快速关系的小分数因数(<1/2)或导致接地关系的大分数因数(> 1/2)时,以减小的方式控制PLL反馈信号的自校正分数延迟元件。带有延迟线环(DLL)的小数N锁相环(PLL)。

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