A device that detects and executes traps on superscalar processors

摘要

An apparatus for detecting and executing trapping program instructions in a superscalar processor operating on a plurality of pipelined instructions includes a fetch term fetching a sequence of instructions from or from the instruction cache 210, And an instruction decode stage (230) for removing instructions from the FIFO memory in accordance with the state ages of the instructions stored in the FIFO memory (220), the decode stage comprising: Checks the command removed from the FIFO memory 220 and flushes all less old instructions from the FIFO memory 220 in response to identifying a trap in the instruction. The decode stage 230 distinguishes between hardware traps and software traps. The software trapping command is sent to the execution end for execution. This decode stage 230 allows the fetch address to be changed to a suitable trap adjuster address.