MULTILAYER PILLAR ARRAY CAPACITOR STRUCTURE FOR DEEP SUB-MICRON CMOS

摘要

The present invention relates to a capacitor structure having an array of electrically conductive pillars forming a flat plate of a capacitor, in particular a capacitor structure used in deep submicron CMOS. Each pillar is formed by electrically conductive line segments from at least two different conductor levels electrically connected by electrically conductive vias. A dielectric material is positioned between the two conductor levels and the pillars of the array. The pillar is electrically connected in an alternating manner to the opposite node so that the pillar is electrically interdigitated.