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Method for fabricating the sub-50 nm-channel MOSFET

机译:低于50 nm沟道MOSFET的制造方法

摘要

The present invention is to act as a micro-channel directed towards a method of manufacturing a device, in particular, the main difference in the gate and the work function of I channel by using a side gate formed below the side gate thin source / drain regions, it is an object to reduce the doping of the channel region to improve the mobility of the carrier and provide manufacturing bangbeopreul the micro-channel device that allows to minimize the change in threshold voltage caused by non-uniformity of the implanted impurities for threshold voltage adjustment .; According to the present invention, the method comprising the method of manufacturing a micro-channel device, define a p + polysilicon gate week using a micro-patterning technique after forming the gate oxide film on a p- substrate; Defining the n + polysilicon side gate through an insulating film after the icing on the results, the main gate and the insulating film; And then implanting p 0 halo ions on both sides of the gate side, there is provided a method of manufacturing a micro-channel device formed by including the step of implanting the source / drain n + ion.
机译:本发明用作针对器件制造方法的微通道,特别是,通过使用在侧栅极薄源极/漏极下方形成的侧栅极,栅极的主要区别和I沟道的功函数。区域,目的是减少沟道区域的掺杂以改善载流子的迁移率,并提供制造bangbeopreul的微沟道器件,该器件允许最小化由于阈值所注入的杂质的不均匀性引起的阈值电压的变化。电压调整根据本发明,该方法包括制造微通道器件的方法,在p-衬底上形成栅氧化膜之后,使用微图案化技术限定p +多晶硅栅周;以及结冰后,通过绝缘膜定义n +多晶硅侧栅,主栅和绝缘膜;然后在栅极侧的两侧上注入p 0 卤离子,提供了一种制造微通道器件的方法,该方法包括注入源/漏n +离子的步骤。

著录项

  • 公开/公告号KR100319449B1

    专利类型

  • 公开/公告日2002-01-05

    原文格式PDF

  • 申请/专利权人 NULL NULL;

    申请/专利号KR19990012742

  • 发明设计人 신형철;이종호;한상연;

    申请日1999-04-12

  • 分类号H01L21/334;

  • 国家 KR

  • 入库时间 2022-08-22 00:30:01

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