METHOD FOR DEADLOCK RESOLUTION AND COMPUTER SYSTEM DEADLOCK REQUEST RESOLUTION

摘要

One or more shared storage controller (SC) a plurality of central processor connected to the device (CPs) in the multiprocessor system consisting of input and output adapter requester (requester) between the potential deadlock (potential deadlock) the detection and to avoid discloses a hardware mechanism were (開 示). It needs to go to each memory controller may originate from outside sources, such as the internal source (source) as well as, CPs, input and output adapters, and other hardware equipment, such as the SC is used to store and fetch between the SC and the main memory processing. All requirements must be used to prioritize the flowchart is given priority before starting the run should be prioritized. Particular order of demand may lead to a deadlock (deadlock), require that the lock-out (locking out) or that has a lower priority because they use their priority cycle demand having a high priority, and any priority level, with the result required with the resources needed to complete the other requirements for. Herein in a deadlock resolution mechanism described in the present invention, checking the request register valid bit and uses the time pulses (timed pulse) a part of the pulse is used to detect the hang-up in the SC, the request is completed in the storage controller check the length of time spent in a valid state is not. A request register valid bit is turned on (on) for, when the two time pulse has been received is set in the internal latch hang-up detection. If at some point, whether the valid bit is reset, the detection logic and the internal hangup detection latch is reset. When the internal hangup detection latch set, the ongoing demand until the demand inside the hang-up is detected completion is allowed to be completed, a new request is pending in an inactive state (inactive state).