Clock signal generator uses discrete timing oscillator and comparison of signal phase of discrete timing output signal with phase of highest value bits of latter signal for phase correction

摘要

The clock signal generator (1) has a discrete timing oscillator (4) controlled by an input clock signal and providing a periodic digital discrete timing output signal. This is compared in phase with the phase of the highest value bits of the discrete timing output signal, with subsequent reduction of the phase disparity, for supplying the phase corrected highest value bit to the clock signal generator output (41) as the output clock signal.