Faulty memory cell address reduction method compares each detected faulty memory cell address with second fault address for word and/or bit line to be repaired for eliminating duplications

摘要

The method reduces the number of memory cell addresses which are stored and processed during testing of a memory (3) by comparing a faulty memory cell address obtained by testing with a second fault address for a word and/or bit line to be repaired, with the faulty memory cell address only stored when it does not correspond to the second fault address. An Independent claim for a device for reducing the number of faulty memory cell addresses during testing of a memory is also included.