Test circuit for cycling ferroelectric memory cells of integrated ferroelectric memory component writes to several ferroelectric memory cells simultaneously in test mode

摘要

The circuit (1a) is in the form of a digital circuit integrated into the ferroelectric memory component and is designed to write to several ferroelectric memory cells (Z) simultaneously in test mode, whereby read amplifiers (LV1,LV2) used in normal mode are deactivated or isolated from bit lines (BL1,..) of a cell field of the ferroelectric memory component by electronic switches. Independent claims are also included for the following: a ferroelectric memory component.