首页> 外国专利> Brief description of embodiments of a circuit comprising an insulation adjoining has an active zone of a transistor, and the corresponding circuit integrated

Brief description of embodiments of a circuit comprising an insulation adjoining has an active zone of a transistor, and the corresponding circuit integrated

机译:包括绝缘体的电路的实施例的简要说明,绝缘体具有晶体管的有源区,并且相应的电路被集成

摘要

Method comprises formation of set of layers on substrate (1) including insulating layer (20) and stop layer with remaining portions (31), stage of formation of block of insulating material (MI) in trench (7) including etching of set of layers, formation of trench in substrate by etching, filling of trench with insulating material, and finishing stage. Finishing stage includes, prior to the formation of the gate oxide (OXG) on the active zone of transistor, the stages of surface oxide removal reducing the height of the block of insulating material formed in the trench. The etching of the set of layers includes a lateral etching of the stop layer along perimeter of the opening of the trench (7) to a lateral distance (d) chosen with respect to the height reduction in the finishing stage so that the block of insulating material filling the trench does not have a depression with respect to the level of gate oxide, or that the level of localised depression is less than 10 nm in depth. The block of insulating material (MI) does not extend to the active zone, or extends to the active zone to a distance less than 15 nm. The lateral distance (d) of etching can be equal to 10 nm, and not greater than 40 nm. The lateral etching of the stop layer formed of eg. silicon nitride, is carried out after the trench etching and before the filling of trench. A layer of material with remaining portions (40), of different material as eg. tetraethylorthosilicate (TEOS), is deposited on the stop layer, and the etching of the set of layers is anisotropic with use of a resin mask deposited on the upper layer. An opening of the resin mask corresponds to the opening of trench, and the lateral etching is isotropic with use of preliminary etched upper layer as a mask. The upper layer with remaining portions (40) is removed before the filling of trench. The insulating layer with remaining portions (20) is formed of eg. silicon dioxide.
机译:该方法包括在包括绝缘层(20)和具有其余部分(31)的停止层的衬底(1)上形成一组层,在沟槽(7)中形成绝缘材料块(MI)的步骤,包括蚀刻该组层通过蚀刻在衬底中形成沟槽,用绝缘材料填充沟槽以及完成阶段。精整阶段包括在晶体管的有源区上形成栅极氧化物(OXG)之前,去除表面氧化物的阶段将减小在沟槽中形成的绝缘材料块的高度。对这组层的蚀刻包括沿着沟槽(7)的开口的周长对停止层进行横向蚀刻,直到在精加工阶段相对于高度减小选择的横向距离(d),以使绝缘块填充沟槽的材料相对于栅极氧化物的水平没有凹陷,或者局部凹陷的深度小于10 nm。绝缘材料块(MI)不会延伸到有源区,也不会延伸到有源区小于15 nm的距离。蚀刻的横向距离(d)可以等于10nm,并且不大于40nm。停止层的横向蚀刻由例如氮化硅形成。氮化硅在沟槽蚀刻之后和沟槽填充之前进行。具有其余部分(40)的材料层,其具有例如不同的材料。将原硅酸四乙酯(TEOS)沉积在停止层上,并使用沉积在上层的树脂掩膜对各组层进行各向异性刻蚀。树脂掩模的开口对应于沟槽的开口,并且通过使用初步蚀刻的上层作为掩模,横向蚀刻是各向同性的。在填充沟槽之前,去除具有剩余部分(40)的上层。具有剩余部分(20)的绝缘层由例如碳纳米管形成。二氧化硅。

著录项

  • 公开/公告号FR2792113B1

    专利类型

  • 公开/公告日2002-08-09

    原文格式PDF

  • 申请/专利权人 STMICROELECTRONICS SA;

    申请/专利号FR19990004269

  • 发明设计人 DE COSTER WALTER;INARD ALAIN;

    申请日1999-04-06

  • 分类号H01L21/762;H01L29/786;

  • 国家 FR

  • 入库时间 2022-08-22 00:24:35

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