Circuit for filtering parasitic logic signals, for use as buffer circuit for filtering external clock signal supplied to serial memory store, in information technology

摘要

The filter circuit (10) designed for filtering a variation of input logic signal (DIN) of duration below a predetermined threshold value (Tf), comprises the means for delivering two signals (DH,DL) of saw-tooth waveform when the input signal changes its value, which includes two inverter gates (S1,S2), two resistors (R1,R2), two capacitors (C1,C2), and two transistors-interrupters (T1,T2) of MOS type, two logic circuits (S3,S4) with switching threshold (Vth) receiving the two sawtooth signals (DH,DL), and the storage means in the form of flip-flops (FF1,FF2) delivering an output signal (DOUT) having a first logic value when the signals (SET1,RST1) output by logic circuits (S3,S4) have a first couple of values, and a second logic value when the output signals of logic circuits have a second couple of values. The first memory circuit (FF1) receives on its inputs R,S (Reset, Set) the signals (RST1,SET1) output by logic circuits (S3,S4) and delivers on its outputs, inverted and direct, /Q,Q, the signals (SET2,RST2) which are received by the second memory circuit (FF2) on inputs S,R, and are combined to produce at output Q the output signal (DOUT). The slopes of two signals (DH,DL) are substantially equal, as well as the switching thresholds of logic circuits (S3,S4). The RC analogue circuits are for charging or discharging the capacitors (C1,C2), and the transistors (T1,T2) are for discharging or charging the capacitors when the first or second signal (DH,DL) has to be restored to its initial value. The analogue circuit (R2,C2) delivering the first signal (DH) receives an inverted logic signal (IN1), and the analogue circuit (R1,C1) delivering the second signal (DL) receives a logic signal (IN2). The logic circuits (S3,S4) are inverters with a switching hysteresis, preferentially of the Schmitt trigger type. An integrated circuit comprises a filter circuit as proposed for use as a buffer circuit at an external clock signal input. The method for filtering a variation of input signal which is shorter than a predetermined threshold value, consists in generating the saw-tooth signals (DH,DL), applying obtained signals to the logic circuits (S3,S4), and generating the output signal (DOUT) by use of memory circuits (FF1,FF2).