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Microprocessor with an architecture mode control capable of supporting extensions to two distinct instruction set architecture
Microprocessor with an architecture mode control capable of supporting extensions to two distinct instruction set architecture
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机译:具有架构模式控制的微处理器,能够支持对两种不同指令集架构的扩展
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摘要
A microprocessor which supports two distinct instruction-set architectures. The microprocessor includes a mode control unit which enables extensions and/or limitations to each of the two architectures and controls the architectural context under which the microprocessor operates. The control unit controls memory management unit (MMU) hardware that is designed to allow address translation to take place under the control of a mode bit so that the translation mechanism can be switched from one architecture to another. A single MMU translates addresses of the two distinct architectures under control of the mode bit which is also used to simultaneously inform instruction decode which architecture is being used so that instructions are properly decoded. The MMU is also capable of mapping the address translation of one architecture onto that of the other so that software written for both architectures may be multi-tasked under the control of a single operating system. IMAGE
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