首页> 外国专利> Inspection pattern of semiconductor equipment and manufacturing process management manner null

Inspection pattern of semiconductor equipment and manufacturing process management manner null

机译:半导体设备检查模式及制造过程管理方式为空

摘要

PROBLEM TO BE SOLVED: To detect under polishing and over polishing accurately, when a buried interconnection is formed through chemical-mechanical polishing.;SOLUTION: An isolation pattern 112 comprising an embedded conductive film is provided on a lower layer interconnection layer. A recess is formed in the pattern 112 by dishing. Consequently, the recess is transferred onto an interlayer insulation film, on which an upper layer interconnection layer is formed. When under polishing occurs in the polishing process of the upper layer interconnection layer, a metal of the second interconnection layer is left in the transferred recess and detected by means of an SEM and the like, thus detecting under polishing.;COPYRIGHT: (C)2001,JPO
机译:解决的问题:当通过化学机械抛光形成掩埋互连时,为了准确地检测抛光不足和过度抛光。解决方案:在下层互连层上提供包括嵌入式导电膜的隔离图案112。通过凹陷在图案112中形成凹槽。因此,凹部被转印到层间绝缘膜上,在该层间绝缘膜上形成有上层互连层。当在上层互连层的抛光过程中发生欠抛光时,第二互连层的金属留在转移的凹槽中,并通过SEM等进行检测,从而进行欠抛光检测。 2001年

著录项

  • 公开/公告号JP3440920B2

    专利类型

  • 公开/公告日2003-08-25

    原文格式PDF

  • 申请/专利权人 松下電器産業株式会社;

    申请/专利号JP20000117501

  • 发明设计人 野口 周平;

    申请日2000-04-19

  • 分类号H01L21/3205;H01L21/304;H01L21/66;

  • 国家 JP

  • 入库时间 2022-08-22 00:22:08

相似文献

  • 专利
  • 外文文献
  • 中文文献
获取专利

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号