Output circuit for double data rate dynamic ram, method, and data strobe signal offer method of data removing from the double data rate dynamic ram and double data rate dynamic ram

摘要

(57) Abstract The external clock same period it did the output data and the method and the device in order to make the data strobe signal synchronize, the internal interleave clock pulse inside double data rate (DDR) DRAM is used. Delay locked loop inside DDR DRAM is locked by the external clock pulse, generates the internal interleave clock pulse. The internal interleave clock pulse through the timing circuit where reitenshi and the bursting long selecting signal are connected when being spread, is delayed is adjusted in the external clock pulse. The data strobe signal is formed making use of the clock pulse from delay locked loop, internal interleave clock pulse is synchronized. The data strobe signal and the data are bonded, the external clock pulse and the output data which possesses specified delay relationship and in order to offer the data strobe signal, through similar number and the plural passes which possess the delay element of type.