SYSTEM HAVING READ MODIFYING WRITE UNIT

摘要

PPROBLEM TO BE SOLVED: To improve throughput by processing a succeeding CPU command in parallel to read modifying write processing. PSOLUTION: A processor has a CPU 1 for executing the command, a memory 2 for storing information, a BIU 3 for starting a read bus cycle, a write bus cycle, and a dummy bus cycle of none of these for the memory with the memory, and an RMWU 10 between the CPU 1 and the BIU 3. The RMWU ha a storage means 12 for storing a modifying condition outputted from the CPU 1, a means 13 for forming modifying data on the basis of this modifying condition, a storage means 14 for storing read data outputted from the BIU 3, an arithmetic operation means 15 for executing a modifying operation according to an arithmetic operation control signal on the basis of the read data from this storage means 14 and the modifying data from the modifying data forming means 13, and a storage means 17 for storing write data determined from write data from the CPU 1 and an arithmetic operation result of the arithmetic operation means 15. PCOPYRIGHT: (C)2003,JPO