EARLY DELAY ANALYSIS SYSTEM IN HIERARCHICAL LAYOUT AND DELAY ANALYSIS PROGRAM

摘要

PROBLEM TO BE SOLVED: To perform delay analysis before completion of the entire layout of an LSI (large-scale integrated circuit).;SOLUTION: An early delay analysis system in hierarchical layout comprises an RC merge/hierarchical development means 21 for outputting the entire chip net list 13 formed by merging RC information of a net extending over a macro boundary from a low-order hierarchy net list 12 and a top net list 12 including macro circuit information, approximate wiring information and its RC information, performing macro development and eliminating macro hierarchy, a delay information generation means 22 for outputting wiring delay and gate delay information 15 by every net by referring to a primitive block delay library 14 and a delay analysis means 23 for inputting the delay information 15, the entire chip net list 13 and delay restriction information 16 and for outputting frequency distribution statistical information by every delay restriction violation path and violation value as delay analysis information 17.;COPYRIGHT: (C)2004,JPO