首页> 外国专利> BIT LINE CONTROL DECODER CIRCUIT, VIRTUAL GROUND TYPE NONVOLATILE SEMICONDUCTOR MEMORY PROVIDED WITH IT, AND READ-OUT METHOD FOR VIRTUAL GROUND NONVOLATILE SEMICONDUCTOR MEMORY

BIT LINE CONTROL DECODER CIRCUIT, VIRTUAL GROUND TYPE NONVOLATILE SEMICONDUCTOR MEMORY PROVIDED WITH IT, AND READ-OUT METHOD FOR VIRTUAL GROUND NONVOLATILE SEMICONDUCTOR MEMORY

机译:位线控制解码器电路,其提供的虚拟接地型非易失性存储器以及虚拟接地非易失性存储器的读出方法

摘要

PROBLEM TO BE SOLVED: To realize high speed read-out by suppressing effectively a leak current of an adjacent cell in a virtual ground type nonvolatile semiconductor memory.;SOLUTION: At the time of read-out operation, a ground potential GND is applied to a bit line SBL5 connected to a source region of one memory cell transistor MC04 being object of read-out. Also, a read-out drain bias potential Vread is applied to a bit line SBL4 connected to a drain region of the memory cell transistor MC04. A bit line SBL3 connected to a drain region of a first adjacent memory cell transistor is made a floating state. The same potential Vdb as a read-out drain bias potential Vread is applied to a bit line SBL2 connected to a drain region of a second adjacent memory cell transistor MC02.;COPYRIGHT: (C)2003,JPO
机译:解决的问题:通过有效地抑制虚拟接地型非易失性半导体存储器中相邻单元的泄漏电流来实现高速读出。解决方案:在读出操作时,将地电势GND施加到连接到作为读出对象的一个​​存储单元晶体管MC04的源极区域的位线SBL5。另外,将读出的漏极偏置电位Vread施加到连接到存储单元晶体管MC04的漏极区域的位线SBL4。连接到第一相邻存储单元晶体管的漏极区域的位线SBL3成为浮置状态。与读出的漏极偏置电势Vread相同的电势Vdb施加到连接到第二相邻存储单元晶体管MC02的漏极区域的位线SBL2。版权所有:(C)2003,JPO

著录项

  • 公开/公告号JP2003100092A

    专利类型

  • 公开/公告日2003-04-04

    原文格式PDF

  • 申请/专利权人 SHARP CORP;

    申请/专利号JP20010296435

  • 发明设计人 ITO NOBUHIKO;YAMAMOTO KAORU;

    申请日2001-09-27

  • 分类号G11C16/06;G11C16/04;

  • 国家 JP

  • 入库时间 2022-08-22 00:20:20

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