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WIRING MODELING METHOD, WIRING MODEL, METHOD FOR EXTRACTING WIRING MODEL AND METHOD FOR DESIGNING WIRING

机译:布线建模方法,布线模型,提取布线模型的方法和设计布线的方法

摘要

PROBLEM TO BE SOLVED: To solve such a problem that although wiring to be formed on a semiconductor chip is affected by a manufacturing process, and the finish dimensions after manufacturing deviates from design values, any method for estimating the deviation, and for precisely reflecting it on the design is not developed. SOLUTION: Wiring 105 to be measured is placed at the center, and wiring width W, wiring interval S, wiring formation region X/Y, and data ratio D of wiring to be actually wired in the wiring formation region XY are variably changed so that the test pattern of wiring can be prepared. The cross-sectional shape and resistance value of the wiring 105 to be measured are measured, and one side thinning quantity Ba against the wiring width W, wiring side face inclination A, wiring side face barrier metal film thickness Ths, wiring bottom face barrier metal film thickness Thb, wiring part film thickness Tcu, and film thickness correction value Tr are used as model parameters, and a model formula with each of them as the function of W is extracted so that the wiring resistance value and inter-wiring capacity can be accurately estimated.
机译:要解决的问题:为了解决以下问题:尽管要在半导体芯片上形成的布线会受到制造工艺的影响,并且制造后的最终尺寸偏离设计值,但是可以使用任何估算偏差并精确反映偏差的方法关于设计未开发。解决方案:将要测量的布线105放置在中心,并且布线宽度W,布线间隔S,布线形成区域X / Y和要在布线形成区域XY中实际布线的数据比率D可变地变化,使得可以准备接线的测试图案。测量要测量的布线105的截面形状和电阻值,并相对于布线宽度W,布线侧面倾角A,布线侧面阻挡金属膜厚度Ths,布线底面阻挡金属相对于一侧的减薄量Ba。将膜厚Thb,配线部膜厚Tcu和膜厚校正值Tr用作模型参数,并提取作为W的函数的模型公式,从而可以得到配线电阻值和配线间容量。准确估算。

著录项

  • 公开/公告号JP2003108622A

    专利类型

  • 公开/公告日2003-04-11

    原文格式PDF

  • 申请/专利权人 NEC CORP;

    申请/专利号JP20010295987

  • 发明设计人 YAMADA KENTA;

    申请日2001-09-27

  • 分类号G06F17/50;H01L21/3205;H01L21/82;

  • 国家 JP

  • 入库时间 2022-08-22 00:18:07

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