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Adaptive sigma-delta modulation with one-bit quantization

机译:具有一位量化的自适应sigma-delta调制

摘要

An adaptive sigma delta modulator has an input stage, a conventional sigma delta modulator, and adaptation stage, and an output stage. The input stage produces a difference signal representing the difference between an analog input signal and an adaptive signal, the amplitude of the analog input signal being in a first range [−a +a]. The conventional sigma delta modulator produces an intermediate digital output sequence representative of the difference signal, the amplitude of the intermediate digital output sequence being in a second range [−b +b], wherein ba. The adaptation stage produces the adaptive feedback signal such that the amplitude of the adaptive signal keeps the difference signal within the second range [−b +b]. The output stage produces a final digital output sequence that is the sum of the intermediate digital output sequence and a delayed adaptive feedback signal representative of the adaptive feedback signal delayed by one sampling clock period. The final digital output sequence has an amplitude in the first range [−a +a] and is a digital representation of the analog input signal delayed by one sampling clock period.
机译:自适应∑-Δ调制器具有输入级,常规的∑-Δ调制器和自适应级以及输出级。输入级产生代表模拟输入信号和自适应信号之间的差的差信号,该模拟输入信号的幅度在第一范围[& a+ a]内。常规的∑-Δ调制器产生代表差信号的中间数字输出序列,该中间数字输出序列的幅度在第二范围[& b+ b&rsqb ;,其中b <a。自适应级产生自适应反馈信号,以使得自适应信号的幅度将差信号保持在第二范围&lsqb& b+ b]内。输出级产生最终的数字输出序列,该数字输出序列是中间数字输出序列与代表延迟了一个采样时钟周期的自适应反馈信号的延迟自适应反馈信号之和。最终的数字输出序列的幅度在第一范围[ -a+ a]中。是延迟一个采样时钟周期的模拟输入信号的数字表示。

著录项

  • 公开/公告号US2003146865A1

    专利类型

  • 公开/公告日2003-08-07

    原文格式PDF

  • 申请/专利权人 ZIERHOFER CLEMENS M;

    申请/专利号US20030357613

  • 发明设计人 CLEMENS M. ZIERHOFER;

    申请日2003-02-04

  • 分类号H03M3/00;

  • 国家 US

  • 入库时间 2022-08-22 00:07:46

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