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Method and system for formal verification of a circuit model using binary decision diagrams
Method and system for formal verification of a circuit model using binary decision diagrams
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机译:使用二进制决策图形式验证电路模型的方法和系统
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摘要
The present invention provides a method and system for comparing a pair of circuit models without the need for performing a false negative check when cut-points are introduced. An exemplary method includes generating a BDD for each of a plurality of signals of each circuit model from an initial cut-point frontier towards an output of each circuit model until a BDD of one of the plurality of signals reaches a predetermined maximum size, selecting a new cut-point signal frontier, and generating a normalized function for each cut-point signal on the new cut-point frontier of each circuit model.
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