Method of reducing shear stresses on IC chips and structure formed thereby

摘要

A method and structure for reducing mechanical shear stresses induced in an IC chip by metal interconnect lines that interconnect the chip with its surrounding substrate. A dielectric layer overlies at least a portion of the substrate and a peripheral surface region of the chip. The lines are formed on the dielectric layer and are electrically interconnected with contact pads on the peripheral surface region of the chip, i.e., beneath the dielectric layer. At least one trench is formed in the dielectric layer and surrounds the peripheral surface region of the chip. The lines traverse the trench so as to have nonplanar portions within the trench. The trenches and the nonplanar portions of the lines increase the expansion/contraction capability of the dielectric layer and lines in a region sufficiently close to where the lines are interconnected to the contact pads, such that shear stresses at critical points near the line-pad connections are significantly reduced.