Method and apparatus for repeating (extending) transactions on a bus without clock delay

摘要

A method and apparatus is described that is related to repeating (extending) transactions on a bus. A plurality of buffer pairs are configured to direct a plurality of signals between a first bus and a second bus in a bus cycle. A circuit is configured to monitor a control signal to determine a bus location of a master device and the circuit is further configured to enable one buffer in the buffer pairs to control a direction of the plurality of signals between the first bus and the second bus.