System for accessing shared memory by two processors executing same sequence of operation steps wherein one processor operates a set of time later than the other

摘要

A data processing system comprising a common memory shared by a first and second data processor circuit, in which each processor circuit executes the same sequence of operational steps and each is connected to the common memory. An isolating device connected between the first data processor circuit and the common memory restricts access by the processor circuit is arranged to execute each operational step a set time period later than the second data processor circuit. A comparator compares the output signals of the two processor circuits in order to detect faulty operation but, before the comparison, the outputs of the second processor circuit are delayed by the set time period.