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Testing system for evaluating integrated circuits, a testing system, and a method for testing an integrated circuit

机译:用于评估集成电路的测试系统,测试系统以及用于测试集成电路的方法

摘要

A burn-in testing system for evaluating a circuit under test, the system including a burn-in board having a plurality of receptacles, at least one of which being sized to receive the circuit under test, test interface circuitry supported by the board and coupled to the receptacles, the test interface circuitry including a transmitter and receiver; power conductors supported by the board, coupled to the receptacles and configured to be connected to a power supply to power the circuit under test during burn-in testing, control and data signal conductors, a burn-in oven having a compartment selectively receiving the burn-in board and being configured to apply heat within the compartment, and an interrogator unit supported by the burn-in oven, the interrogator unit being configured to send commands to the test interface circuitry to exercise the circuit under test optically or via radio communication and to receive responses to the commands optically or via radio communication. A method for testing an integrated circuit having operational circuitry formed thereon, optically and via radio frequency.
机译:一种用于评估被测电路的老化测试系统,该系统包括具有多个插座的老化板,其中至少一个插座的尺寸设计成可容纳被测电路,该板支撑并耦合了测试接口电路到插座,测试接口电路包括发射机和接收机;由板支撑的电源导体,耦合到插座,并配置为在老化测试,控制和数据信号导体期间连接到电源以为被测电路供电,老化烤箱具有选择性地接收灼伤的隔间-内置板并被配置为在车厢内加热,以及由老化炉支撑的询问器单元,该询问器单元被配置为向测试接口电路发送命令,以光学方式或通过无线电通信对被测电路进行测试;以光学方式或通过无线电通信接收对命令的响应。一种用于测试集成电路的方法,该集成电路具有光学地和经由射频形成于其上的运算电路。

著录项

  • 公开/公告号US6484279B2

    专利类型

  • 公开/公告日2002-11-19

    原文格式PDF

  • 申请/专利权人 MICRON TECHNOLOGY INC.;

    申请/专利号US20020057635

  • 发明设计人 SALMAN AKRAM;

    申请日2002-01-23

  • 分类号G01R312/80;

  • 国家 US

  • 入库时间 2022-08-22 00:06:22

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