A SERDES (serializer/deserializer) time domain multiplexer/demultiplexer multiplexes N input signals into a single output signal. In multiplexing the N input signals, each input signal utilizing its respective clock is latched in a respective one of N latches whose respective outputs are respectively inputted into N circular buffers. The outputs of the N circular buffers are inputted to a multiplexer whose output is outputted to a latch. In demultiplexing an input signal into N output signals, the input signal is latched in N respective latches whose outputs are inputted to N respective circular buffers. The outputs of the N respective circular buffers are inputted to N respective output latches. The N output latches are clocked by N respective output clock inputs which are different from the N respective input clocks used to clock the N respective input latches.
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