首页>
外国专利>
Time-division multiplexing data aggregation over high speed serializer/deserializer lane
Time-division multiplexing data aggregation over high speed serializer/deserializer lane
展开▼
机译:高速串行器/解串器通道上的时分多路复用数据聚合
展开▼
页面导航
摘要
著录项
相似文献
摘要
A digital signal interface includes a multiplexer coupled to receive a plurality of data signals from at least one of a microprocessor, a microcontroller, or a field-programmable gate array (FPGA), the multiplexer multiplexing the plurality of data signals. The interface further includes a serializer/deserializer (SerDes) transceiver coupled to receive the multiplexed data signals, the SerDes transceiver serializing the multiplexed data signals and transmitting the serialized data signals.
展开▼