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Time-Division Multiplexing Data Aggregation Over High Speed Serializer/Deserializer Lane
Time-Division Multiplexing Data Aggregation Over High Speed Serializer/Deserializer Lane
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机译:高速串行器/解串器通道上的时分复用数据聚合
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摘要
A digital signal interface includes a multiplexer coupled to receive a plurality of data signals from at least one of a microprocessor, a microcontroller, or a field-programmable gate array (FPGA), the multiplexer multiplexing the plurality of data signals. The interface further includes a serializer/deserializer (SerDes) transceiver coupled to receive the multiplexed data signals, the SerDes transceiver serializing the multiplexed data signals and transmitting the serialized data signals.
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