Simulation circuit for MOS transistor, simulation testing method, netlist of simulation circuit and storage medium storing same

摘要

A simulation circuit for MOS transistors is provided in which neither oscillation nor a change in a characteristic of feedback capacitance occurs. A ratio of a junction capacitance characteristic of a third diode and an electrostatic capacity characteristic of a capacitor to be displayed, changes in response to a change in a voltage between a drain and a gate and the junction capacitance characteristic of the third diode and the electrostatic capacity characteristic of the capacitor are displayed at an equal ratio in a region where a voltage between the drain and gate is almost 0 (zero) V and, therefore, normal simulation testing can be done and no oscillation occurs. Moreover, since no resistor component is connected in series in the third diode and the capacitor, there is no time constant. Therefore, a characteristic curve of the feedback capacitance can be normally obtained irrespective of the change rate of the voltage between the drain and gate.