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Method and apparatus for reducing power consumption by skipping second accesses to previously accessed cache lines

机译:通过跳过对先前访问的高速缓存行的第二次访问来减少功耗的方法和设备

摘要

A digital data processing system is provided which includes a digital data processor, a cache memory having a tag RAM and a data RAM, and a controller for controlling accesses to the cache memory. The controller stores state information on access type, operation mode and cache hit/miss associated with the most recent access to the tag RAM, and controls a current access to the tag RAM just after the preceding access based on the state information and a portion of a set field of a main memory address for the second access. The controller determines whether the current access is applied to the same cache line that was accessed in the first access based on the state information and a portion of a set field of the main memory address for the second access, and allows the current access to be skipped when the current access is applied to the same cache line that was accessed in the preceding access.
机译:提供了一种数字数据处理系统,其包括数字数据处理器,具有标签RAM和数据RAM的高速缓冲存储器以及用于控制对该高速缓冲存储器的访问的控制器。控制器存储有关访问类型,操作模式和与标签RAM的最近访问相关联的高速缓存命中/未命中的状态信息,并基于状态信息和部分信息来控制在先前访问之后对标签RAM的当前访问。用于第二次访问的主存储器地址的设置字段。控制器基于状态信息和用于第二访问的主存储器地址的设置字段的一部分,确定当前访问是否应用于在第一次访问中访问的同一高速缓存行,并允许当前访问为当前访问应用于先前访问中访问的同一高速缓存行时,将跳过。

著录项

  • 公开/公告号US6560679B2

    专利类型

  • 公开/公告日2003-05-06

    原文格式PDF

  • 申请/专利权人 SAMSUNG ELECTRONICS CO. LTD.;

    申请/专利号US20000742030

  • 发明设计人 HOON CHOI;MYUNG-KYOON YIM;

    申请日2000-12-20

  • 分类号G06F120/80;

  • 国家 US

  • 入库时间 2022-08-22 00:04:13

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