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DRAM including an address space divided into individual blocks having memory cells activated by row address signals
DRAM including an address space divided into individual blocks having memory cells activated by row address signals
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机译:包括地址空间的DRAM,该地址空间被划分为具有通过行地址信号激活的存储单元的各个块
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摘要
A DRAM with an address space divided into blocks, in which storage cells of individual blocks can be activated by a row address signal (RAS) furnished by a controller. Each individual block can then be activated by an independent activation signal derived from the row address signal. The activation signals for different blocks are supplied to the different blocks in succession with a partial time overlap, so that the obtained data rate is increased relative to activation of only one block, owing to partial time activation of at least two different blocks.
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