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IMPROVED COPPER CMP PROCESS UTILIZING DUMMY PLUGS IN DAMASCENE PROCESS

机译:利用DAMASCENE工艺中的虚拟塞子改进了铜CMP工艺

摘要

ABSTRACTIMPROVED COPPER CMP PROCESS UTILIZING DUMMY PLUGS IN DAMASCENE PROCESSA method of fabricating a semiconductor wafer having at least one integrated circuit, the method comprising the following steps. A semiconductor wafer structure having at least an upper and a lower dielectric layer is provided. The semiconductor wafer structure having a bonding pad area and an interconnect area. At least one active interconnect having a first width is formed in the interconnect area, through the dielectric layers. A plurality of adjacent dummy plugs each having a second width is formed in the bonding pad area, through a portion of the dielectric layers. The semiconductor wafer structure is patterned and etched to form trenches through the upper dielectric layer. The trenches surround each of the at least one active interconnect and the dummy plugs whereby the upper dielectric level between the adjacent dummy plugs is removed. A metallization layer is deposited over the lower dielectric layer, filling the trenches at least to the upper surface of the remaining upper dielectric layer. The metallization layer is planarized to remove the excess of the metallization layer forming a continuous bonding pad within the bonding pad area and including the plurality of adjacent dummy, plugs, thus forming at least one damascene structure including the at least one respective active interconnect.Figure 9
机译:抽象利用DAMASCENE工艺中的虚拟塞子改进了铜CMP工艺一种制造具有至少一个集成电路的半导体晶片的方法,该方法包括以下步骤。提供至少具有上介电层和下介电层的半导体晶片结构。半导体晶片结构具有焊盘区域和互连区域。穿过介电层在互连区域中形成具有第一宽度的至少一个有源互连。穿过电介质层的一部分,在接合焊盘区域中形成多个相邻的虚设插头,每个虚设插头具有第二宽度。图案化和蚀刻半导体晶片结构以形成穿过上介电层的沟槽。沟槽围绕至少一个有源互连和虚设插头中的每一个,从而去除了相邻虚设插头之间的上电介质层。在下部介电层上方沉积金属化层,以至少将沟槽填充至其余上部介电层的上表面。将金属化层平坦化以去除多余的金属化层,从而在键合焊盘区域内形成连续的键合焊盘,并包括多个相邻的虚设插塞,从而形成至少一个包括至少一个各自的有源互连的镶嵌结构。图9

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