Electrically erasable and programmable non-volatile memory device with testable redundancy circuits

摘要

An electrically erasable and programmable non-volatile memory device comprises at least one memory sector (S1-S8) comprising an array of memory cells (MC) arranged in rows (WL0-WL255) and first-level columns (BL0-BL255), the first-level columns (BL0-BL255) being grouped together in groups of first-level columns each coupled to a respective second-level column (B1-B64), first-level selection means (2) for selectively coupling one first-level column for each group to the respective second-level column, second-level selection means (3,4) for selecting one of the second-level columns, first direct memory access test means (SW6) activatable in a first test mode for directly coupling a selected memory cell (MC) of the array to a respective output terminal (Oi) of the memory device, redundancy columns (RBL0-RBL3) of redundancy memory cells (RMC) for replacing defective columns (BL0-BL255) of memory cells (MC), and a redundancy control circuit (CAM1-CAM4,5-7,12,SW1-SW5,24) comprising defective-address storage means (CAM1-CAM4) for storing addresses of the defective columns (BL0-BL255) and activating respective redundancy columns (RBL0-RBL3) when the defective columns are addressed. The redundancy control circuit comprises second direct memory access test means (24) activatable in a second test mode together with the first direct memory access test means for directly coupling memory elements (AB0-AB7,GB) of the defective-address storage means (CAM1-CAM4) to respective second-level columns (B1-B64) of the array, whereby the memory elements of the defective-address storage means can be directly coupled to output terminals (Oi) of the memory device. IMAGE