Memory embedded logic integrated circuit mounting memory circuits having different performances on the same chip

摘要

A semiconductor integrated circuit includes a first DRAM circuit (13-1) having a first memory cell array having a plurality of memory cells each including a first MOS transistor, and a first potential generating circuit which generates at least one potential used to operate the plurality of memory cells in the first memory cell array, the first DRAM circuit being formed in a semiconductor chip (11), and a second DRAM circuit (13-2) having a second memory cell array having a plurality of memory cells each including a second MOS transistor different in characteristic from the first MOS transistor, and a second potential generating circuit which generates at least one potential used to operate the plurality of memory cells in the second memory cell array, the second DRAM circuit being formed in the semiconductor chip.